|
The transition to high-level design delivers substantial productivity
and time-to-market advantages. A key component to achieving these
advantages is a methodology that uses transaction-level descriptions as the
link between TLM system-level design and existing RTL-to-GDSII flows.
Cynthesizer provides a state-of-the-art design environment to support such
an integrated ESL-to-GDSII methodology.
 SoC
design starts with a system specification and a collection of platform IP
components that includes processors, busses, and memories. The system
function is partitioned into hardware and software during the architecture
design phase. To explore alternative SoC configurations, hardware functions
can be synthesized with configurable interfaces.
Cynthesizer's TLM Synthesis significantly accelerates the SoC design
exploration process by allowing you to use the same source for both
behavioral synthesis and verification.
It provides the ability to easily switch between alternative
transaction-level and pin-level interfaces, allowing you to fully explore
different communication schemes to achieve optimum system performance.
Using a single TLM source for synthesis and verification allows the
system, software, and hardware design processes to proceed in parallel.
This accelerates all aspects of a SoC design project timeline.
By using Cynthesizer's fully-integrated synthesis, verification, design
management, and process automation environment, you can explore alternative
SoC implementations early in the project. Hardware is generated for
mainstream RTL-to-GDSII flows or FPGA-optimized RTL is created for
concurrent system validation. Cynthesizer produces superior-quality RTL and
reduces back-end iterations.
Cynthesizer helps you manage design risk earlier in the project,
collapse design time, and reduce design cost.
Find out more about high-level design and behavioral synthesis with
Cynthesizer.
|
