"Cliff Cummings' May 5th Letter to the Editor in EDA Weekly brought to
light some of the current confusion surrounding SystemC. Cliff is right
regarding SystemC's scope: It is not intended to create gate-level or RTL
design descriptions. SystemC is meant to permit a single language to be used
for specification, architectural analysis, testbenches, and behavioral
design."
"Many designs today start off as complex algorithms; nearly all of those
algorithms start off in C or C++, and those designers are using SystemC
because it is close to their starting point. So why not just use
SystemVerilog's C interface to do high-level design? Because you can't."
"C/C++ algorithms have no set timing, nor can they be immediately mapped
to hardware blocks because of their lack of a protocol interface. The
SystemVerilog C interface specifically lacks the basic capabilities for
hardware design such as concurrency, hierarchy, and interconnect - it's
'just plain old C!' SystemC adds the prerequisite high-level design
functionality such as hierarchy, cycle accuracy, and bit accuracy. And, by
the way, there is a free simulator at
www.SystemC.org."
"So, 'Where's the beef?' Cliff [Cummings] asks. It is common to observe
10x-100x improvements in simulation performance for algorithms written in
SystemC versus an RTL model. However, even greater value comes from adopting
a high-level design flow, with SystemC used in conjunction with behavioral
synthesis technology. This approach significantly increases designer
productivity, both by reducing time-to-RTL and by speeding verification.
Behavioral synthesis, which has advanced significantly since first
generation tools like BC, lets design engineers focus on designing hardware
- not coding RTL - and SystemC provides the right abstraction level for
that."
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